NFETs using gate induced stress modulation

ABSTRACT

A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 10/667,601, which is incorporated herein by reference in itsentirety.

FIELD OF INVENTION

The invention generally relates to methods for manufacturing asemiconductor device with improved device performance, and moreparticularly to methods for manufacturing semiconductor devices whichimpose tensile and compressive stresses in the substrate of the deviceduring device fabrication.

BACKGROUND DESCRIPTION

Mechanical stresses within a semiconductor device substrate can modulatedevice performance. That is, stresses within a semiconductor device areknown to enhance semiconductor device characteristics. Thus, to improvethe characteristics of a semiconductor device, tensile and/orcompressive stresses are created in the channel of the n-type devices,e.g., NFETs and/or p-type devices, e.g., PFETs. However, the same stresscomponent, either tensile stress or compressive stress, discriminativelyaffects the characteristics of an n-type device and a p-type device.

In order to maximize the performance of both NFETs and PFETs withinintegrated circuit (IC) chips, the stress components should beengineered and applied differently for NFETs and PFETs. That is, becausethe type of stress which is beneficial for the performance of an NFET isgenerally disadvantageous for the performance of the PFET. Moreparticularly, when a device is in tension (in the direction of currentflow in a planar device), the performance characteristics of the NFETare enhanced while the performance characteristics of the PFET arediminished. To selectively create tensile stress in an NFET andcompressive stress in a PFET, distinctive processes and differentcombinations of materials are used.

For example, a trench isolation structure has been proposed for formingthe appropriate stresses in the NFETs and PFETs, respectively. When thismethod is used, the isolation region for the NFET device contain a firstisolation material which applies a first type of mechanical stress onthe NFET device in a longitudinal direction (parallel to the directionof current flow) and in a transverse direction (perpendicular to thedirection of current flow). Further, a first isolation region and asecond isolation region are provided for the PFET and each of theisolation regions of the PFET device applies a unique mechanical stresson the PFET device in the transverse and longitudinal direction.

Alternatively, liners on gate sidewalls, have been proposed toselectively induce the appropriate strain in the channels of the FETdevices (see Ootsuka et al., IEDM 2000, p. 575, for example). Byproviding liners, the appropriate stress is applied closer to the devicethan the stress applied as a result of the trench isolation filltechnique.

While these methods do provide structures that have tensile stressesbeing applied to the NFET device and compressive stresses being appliedalong the longitudinal direction of the PFET device, they may requireadditional materials and/or more complex processing, and thus, resultingin higher cost. In addition, in the methods described above, forexample, the stresses in the channel are relatively moderate (i.e., forexample, about 200 to about 300 MPa), which provide approximately a 10%benefit in device performance. Thus, it is desired to provide morecost-effective and simplified methods for creating stronger tensile andcompressive stresses in the channels NFETs and PFETs, respectively. Itis further desired to create larger tensile stresses in the channels ofthe NFETs than the tensile stresses created as a result of the knownprocesses described above.

SUMMARY OF THE INVENTION

In a first aspect, this invention provides a method for manufacturing anintegrated circuit comprising a plurality of semiconductor devicesincluding an n-type field effect transistor and a p-type field effecttransistor by covering the p-type field effect transistor with a mask. Aportion of a gate polysilicon of the n-type field effect transistor isoxidized such that tensile mechanical stresses are formed within achannel of the n-type field effect transistor.

In a second aspect, this invention separately provides a method formanufacturing an integrated circuit comprising a plurality ofsemiconductor devices including an n-type field effect transistor and ap-type field effect transistor on a semiconductor wafer by oxidizing aportion of a gate polysilicon of the n-type field effect transistor,such that tensile mechanical stresses are formed within a channel of then-type field effect transistor, without creating additional tensilestresses in a channel of the p-type field effect transistor.

In a third aspect, this invention separately provides an integratedcircuit, including: a p-type transistor having a polysilicon layer andan n-type transistor having a polysilicon layer, wherein, afteroxidation of the polysilicon layer of the n-type transistor, thepolysilicon layer of the n-type transistor has an oxide edge with theshape of a vertical bird's beak.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts desired stress states for PFETs and NFETs;

FIGS. 2(a) through 2(k) depict a process for forming gate MOSFETsaccording to the invention;

FIGS. 3(a) through 3(g) depict a portion of another process for forminggate MOSFETs according to the invention;

FIG. 4 depicts stresses in a silicon structure after oxidation of thegate polysilicon according to the invention; and

FIG. 5 depicts stresses in a silicon structure after etching ofdeposited oxide during oxidation of the gate polysilicon according tothe invention.

DETAILED DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

The invention provides a method for fabricating devices with improvedperformance characteristics. In this invention, oxidation of the gatepolysilicon is used to control the stresses in complimentary metal oxidesemiconductor (CMOS) NFET devices such that their performances areenhanced without degrading the performance of the PFET devices.

In one aspect of the invention, polysilicon of an NFET gate is oxidizedwhile the polysilicon of a PFET gate is masked to prevent thepolysilicon of the PFET from being oxidized. By preventing the oxidationof the polysilicon of the PFET, degradation of hole mobility isprevented. In this aspect, the oxidation of NFET gates creates tensilestresses in the channels of the NFETs without creating tensile stressesin the channel of the PFETs. By oxidizing the gate polysilicon of theNFETs large stresses of about 500 MPa to about 1000 MPa, for example,are formed in a channel of the NFET. In one implementation the stressesare about 700 MPa. By providing tensile stresses to the channel of theNFET without providing tensile stresses in the channel of PFET, thecharge mobility and drive current along the channels of the NFET devicesare enhanced without diminishing the charge mobility and drive currentalong the channels of the PFET devices.

By implementing the stresses using a polysilicon over-etch, thisinvention provides the implementation of stresses which are self-alignedto the gate, whereas in the isolation induced stress structures, thestresses are not self aligned to the gate. This invention also providesstress levels in the silicon under the gate which are much larger thanthe isolation-based or liner-based approaches.

Also, when gates that are confined by oxide fill are used, the expansionof the oxide in the gate stack is relatively confined. Further, when aconfined gate is subjected to oxidation, the gate channel is put undertension. The gate is put under tension because oxide deposited thereonexpands outwardly at the top. This results in compression in the toppart of the isolation. At the same time, by inducing bending stresses atthe bottom part of the isolation, next to the polysilicon under tension,the channel receives large tensile stresses. These stress levels are onthe order of about 500 to about 1000 MPa and these tensile stresses arebeneficial to the NFET drive currents. In this invention, the PFETs aremasked during oxidation of the NFETs so that the creation of tensilestresses from this oxidation step in the PFETs is substantially and/orcompletely prevented in order to not diminish the performance of thePFET. Thus, the invention provides for tensile stresses along thechannel of the NFETs without providing tensile stresses along thechannels of the PFETs to improve the performance of the NFET deviceswithout diminishing the performance of the PFET devices.

FIG. 1 illustrates desired stress states for improving the performanceof PFETs and NFETs (see Wang et al, IEEE Trans. Electron Dev., v. 50, p.529, 2003). In FIG. 1, an NFET and a PFET are shown to have a sourceregion, a gate region and a drain region. The NFET and PFET are shown tohave arrows extending outward from the active area to illustrate tensilestresses. The arrows extending inward toward the PFET device areillustrative of compressive forces. More specifically, the outwardlyextending arrows, shown extending from the NFET, illustrate a tensilestress that is desired in the transverse and longitudinal directions ofthe device. Similarly, the inwardly extending arrows, shown withrelation to the PFET, illustrate a desired longitudinal compressivestress. The range of stresses needed to influence device drive currentsis typically on the order of a few hundred MPa to a few GPa. The widthand the length of the active area of each device is represented by “W”and “L”, respectively. It should be understood that each of thelongitudinal or transverse stress components can be individuallytailored to provide the performance enhancements for both devices (i.e.,the NFET and the PFET).

FIGS. 2(a) through 2(j) depict a general exemplary process for formingthe MOSFETs according to this invention. FIGS. 2(a) through 2(d) explainprocesses that are known, and thus any known applicable processes may beused. FIG. 2(a) illustrates the structure after shallow trenches 5 (STI)are formed. A SOI (silicon-on-insulator) wafer which has a stack ofsilicon 1, buried oxide 2, and a silicon layer 3 is used. Generally, toform the STI on SOI wafers, a thin (˜50 Å) layer of silicon dioxide SiO₂(pad oxide) (not shown) is grown on the silicon layer 3, which is on theburied oxide layer 2 on the silicon substrate 1, by reacting silicon andoxygen at high temperatures. A thin layer (about 1000 Å to about 2500 Å)of pad silicon nitride (Si₃N₄) (not shown) is then deposited usingchemical vapor deposition (CVD). Next, the patterned photoresist with athickness of about 0.5 to about 1.0 microns is deposited, and thestructure is exposed and developed to define the trench areas 5. Next,the exposed SiO₂ and the Si₃N₄ are etched using reactive ion etching(RIE). Next, an oxygen plasma is used to burn off the photoresist layer.A wet etch is used to remove the pad Si₃N₄ and pad oxide. Then, an oxidelayer is deposited to fill the trenches and the surface oxide is removedusing chemical mechanical polishing (CMP). This completes the formationof STI as seen in FIG. 2(a).

Next, a sacrificial oxide (not shown) of about 50 Å is grown on thesilicon. Then, as shown in FIG. 2(b) an n-well 10 and a p-well 12 areformed. Patterned photoresist layers are used to successively form then-well 10 (using, for example, multiple implants of Phosphorous ions)and the p-well 12 (using, for example, multiple implants of Boron ions).The well implants 10 and 12 are then optionally annealed. Thesacrificial oxide layer is then removed using a wet HF solution, suchthat a clean silicon surface is left behind.

Next, as shown in FIG. 2(b), a gate oxide layer 14 of about 10 Å toabout 100 Å is grown. On the gate oxide layer 14, a polysilicon layer 16is deposited using CVD to a thickness of about 500 Å to about 1500 Å toform the gate electrodes 18 and 20 shown in FIG. 2(c). Patternedphotoresist layers (not shown) are used to define the gate electrodes.RIE is used to etch the exposed portions of the polysilicon layer 16 andthe photoresist patterns are stripped away in order to completeformation of the gate stack of the n-type transistor 17 and the gatestack of the p-type transistor 19.

FIG. 2(c) shows the formed gate electrodes 18 and 20. A thin layer ofoxide 15 is then grown on the remaining polysilicon. Patternedphotoresist layers (not shown), which are later removed, are used tosuccessively tip (and halo countering doping implants) implant then-type and p-type transistors. For n-type transistors, a very shallowand low dose implant of arsenic ions, for example, may be used to formthe p-tip 22 (while a Boron implant, for example, may be used forhalos). For p-type transistors, a very shallow and low dose implant ofBF₂ ions, for example, may be used to form n-tip 24 (while an arsenicimplant may, for example, be used for halos).

Still referring to FIG. 2(c), spacers 26 are formed by depositing asilicon nitride layer (not shown) using CVD to a thickness of about 100Å to about 1000 Å and then etching the nitride from the regions otherthan the sidewalls of the gate. Patterned photoresist layers (notshown), which are removed prior to the next stage of the process, areused to successively create the source/drain regions of the transistors.

In FIG. 2(d), for the n-type transistors, a shallow and high-dose ofarsenic ions, for example, may be used to form the source/drain regions28 while the p-type transistors are covered with the correspondingphotoresist layer. For the p-type transistors, a shallow and high doseof BF₂ ions, for example, may be used to form the source/drain regions30 while the n-type transistors are covered with the correspondingphotoresist layer. An anneal is then used to activate the implants. Theexposed oxide on the structure is then stripped by dipping the structurein HF in order to expose bare silicon in the source, gate and drainregions of the transistors.

Still referring to FIG. 2(d), metal or a low resistance material 32 isdeposited to a thickness of about 30 Å to about 200 Å across the wafersurface in order to form silicide. The silicide could be formed fromreacting the underlying with any deposited metal such as Co, Hf, Mo, Ni,Pd2, Pt, Ta, Ti, W, and Zr. In the regions, such as, the source, drainand gate regions, where the deposited metal is in contact with silicon,the deposited metal or low resistance material reacts with the siliconto form silicide. In the other regions (i.e., where the deposited metalis not in contact with silicon), the deposited metal remains unchanged.This process aligns the silicide to the exposed silicon and is called“self-aligned silicide” or salicide.

The unreacted metal is then removed using a wet etch while the formedsilicide 34 remains, as shown in FIG. 2(e). As shown in FIG. 2(e), anoxide fill followed by chemical mechanical polishing is used toplanarize the surface. CMP is used to make the oxide fill flat and suchthat the oxide fill is flushed with the top of the gates. Next, as shownin FIG. 2(f), the silicide 34 on top of the polysilicon is removed usinga selective etch.

In methods according to the invention, the PFET devices of the structureshown in FIG. 2(g) are masked, using a mask 38. The mask 38 may be, forexample, a hard mask, such as for example, a mask made of nitride. Toform the mask 38, nitride, for example, may be deposited on the siliconwafer and the nitride covering the polysilicon gates of the NFETs may beetched to expose the polysilicon gates of the NFETs. The mask exposesthe NFETs so that the additional silicide 34 on the gate polysilicon ofthe NFETs may be etched off from the gate polysilicon of the NFET, asshown in FIG. 2(g).

As shown in FIG. 2(h), the mask 38 covers the PFETs during oxidation ofthe NFETs, such that the gate polysilicon of the PFETs is not oxidizedwhile oxide 40 is deposited on the gate polysilicon of the NFETs.

As also shown in FIG. 2(i), oxidation of the gate polysilicon of theNFETs results in the formation of a vertical bird's beak 44 in the edgeof the polysilicon of the NFETs. The oxidation of the gate of the NFETscreates large tensile stresses in the channel region of the NFETs. Sincethe PFETs are masked, with mask 38, the polysilicon gates of the PFETsare not oxidized. Further, these tensile stresses increase electronmobility along the channel, and improve the performance of the NFETs.The oxidation of the gate polysilicon of the NFETs should be a lowtemperature oxidation, such as, for example, high pressure oxidation,atomic oxidation or plasma oxidation. The oxidation step should beperformed at a low temperature, such as, 600° C. or less in order toprevent degradation of device characteristics, via, for example,deactivation or diffusion. Low temperature oxidation should be used sothat (a) the already created silicide on the source/drain regions doesnot agglomerate and/or change resistivity and (b) so that theextensions, and source and drain dopants do not diffuse and/ordeactivate. Typically, the oxidation should result in about a verticallyformed bird's beak of about 20 Å to about 100 Å in width and height.

As shown in FIG. 2(i), the vertical bird's beak 44 causes the base ofthe polysilicon to be wider than an uppermost surface of the polysiliconand the side edges of the polysilicon taper towards the uppermostsurface thereof. In addition, as shown in FIG. 2(i) in a region wherethe polysilicon tapers towards the uppermost surface, a portion of thegate stack 17 of the NFET comprises a portion of the polysilicon layerand a portion of the deposited oxide forming a vertical bird's beak 44are present along a plane perpendicular to a plane of the base of thepolysilicon. Each vertical bird's beak 44 may have, for example, a widthof about 20 Å to about 100 Å.

As further shown in FIG. 2(j), the oxide above the gate polysilicon ofthe NFETs is etched off while the vertical oxide bird's beak is stillpreserved. The stresses created in the gate polysilicon of the NFETs aremaintained even after removal of this oxide on top of the polysilicon asa result of the vertical bird's beak formed in the gate polysilicon ofthe NFETs because of the oxidation step, as shown in Figures and 5. Asalso shown in FIG. 2(j), the mask 38 has been removed.

Then, as shown in FIG. 2(k), silicide forming material 46 is depositedon the polysilicon gate of the NFETs after removing the mask 38.Material, such as, for example, Co, HF, Mo, Ni, Pd₂, Pt, Ta, Ti, W, andZr may be used to form the silicide When material, such as, for example,Co, HF, Mo, Ni, Pd₂, Pt, Ta, Ti, W, and Zr is deposited on silicon, thesilicon reacts with the material and silicide is formed. The materialfor forming silicide may be deposited over the wafer via, for example,evaporation, sputtering, or CVD techniques. Next, the structure isheated to temperature of about 300° C. to about 700° C. to allow thedeposited silicide material to react with the polysilicon. Duringsintering, silicide only forms in the regions where metal is in directcontact with silicon or polysilicon. The remaining unreacted silicidematerial is then removed, for example, with a selective etch withoutdamaging the formed silicide. After this, the standard middle of theline (e.g. passivation and contact formation) and back end of the line(various interconnect metal, via, and interlevel dielectrics) processesare performed.

In another embodiment of the invention, a nitride cap may be provided onthe gate polysilicon of the NFET instead of the metal or low-resistancematerial. For ease of discussion, the portions of the process which arethe same as the processes described with regard to FIGS. 2(a)-2(k) willnot be repeated below. In this embodiment, the description of thestructure illustrated in FIGS. 2(a) and 2(b) applies to the structureillustrated in FIGS. 3(a) and 3(b). Then, as shown in FIG. 3(c), anitride layer 17 is deposited on the surface. As shown in FIG. 3(d),spacers 26 are formed by depositing a silicon nitride layer using CVD toa thickness of about 100 Å to about 1800 Å and then etching the nitridefrom the regions other than the sidewalls of the gate. The nitride cap19, above the polysilicon of the NFET and PFET is retained.

As shown in FIG. 3(e), silicide forming material 32 is deposited on thesurface. As discussed above, a metal or a low resistance material 32 isdeposited to a thickness of about 30 Å to about 200 Å across the wafersurface in order to form silicide 34 (see FIG. 3(f)). Silicide is formedin the source and drain regions of the transistors (i.e., where thesilicide is in contact with the silicon) and the unreacted material isremoved. As shown in FIG. 3(g), an oxide fill 36 followed by chemicalmechanical polishing is used to planarize the surface. CMP is used tomake the oxide fill flat and such that the oxide fill is flushed withthe top of the gates.

Next, in this embodiment, the nitride caps 19 are stripped off from thepolysilicon gates of the transistors. In methods according to theinvention, the PFET devices of the structure shown in FIG. 3(g) aremasked, using a mask 38. The description of FIGS. 2(g) through 2(k)applies for the remainder of the process.

FIG. 4 shows the stresses in the gate structure after oxidation of thegate polysilicon of the NFET. The dashed lines represent tensile stressand the solid lines represent compressive stress. As can be seen fromFIG. 4, tensile stresses are present in the channel area of the NFET. Instructure illustrated in FIG. 4, tensile stresses of about 1 GPa andless are present in the channel area of the NFET.

FIG. 5 shows the stresses in the gate structure when the oxide above thegate polysilicon is etched in accordance with this invention. This etchis needed since the gate polysilicon has to be silicided for contactformation later. Similar to FIG. 4, the dashed lines represent thetensile stress and the solid lines represent the compressive stress. Ascan be seen from FIG. 5, the stresses in the NFET device is maintainedeven after etching of the oxide from above the gate polysilicon.

The tensile stresses in the NFET device is maintained even after etchingof the oxide due to the formation of the vertical bird's beak in thegate polysilicon as a result of the oxidation of the gate polysilicon.The desired stresses are tensile and add values of the order of 200 MPaand above.

By providing tensile stresses to the channel of the NFET and withoutcreating additional tensile stresses in the channel of the PFETs, thecharge mobility along the channels of NFET devices is enhanced while thehole mobility along the channels of the PFET devices is maintained.Thus, as described above, the invention provides a method for providingtensile stresses along the longitudinal direction of the channel of NFETdevices by oxidizing the polysilicon gate of the NFET devices aftersilicidation of the gate polysilicon.

It should be understood that this invention is readily applicable tobulk or layered SiGe substrates. It should also be understood that thisinvention may also be used with damascene gate structures, which havebeen proposed for use of high k dielectric gate oxides.

While the invention has been described in terms of embodiments, thoseskilled in the art will recognize that the invention can be practicedwith modification within the spirit and scope of the appended claims.

1. An integrated circuit, comprising: a p-type transistor having apolysilicon layer; and an n-type transistor having a polysilicon layer,wherein, after oxidation of the polysilicon layer of the n-typetransistor, the polysilicon layer of the n-type transistor has an oxideedge with the shape of a vertical bird's beak.
 2. The device of claim 1,wherein the vertical bird's beak has a width and height of about 20 Å toabout 100 Å.
 3. The device of claim 2, wherein the polysilicon layer isa gate which has a base which is wider than an uppermost surface thereofand side edges taper towards the uppermost surface thereof.
 4. Thedevice of claim 3, wherein in a region where the polysilicon layertapers towards an uppermost surface, at least a portion of thepolysilicon layer and a portion of an oxide layer are present along aplane perpendicular to a plane of the base of the polysilicon layer. 5.The device of claim 1, wherein the bird's beak is formed between thepolysilicon layer of the n-type transistor and a spacer of the n-typetransistor.
 6. The device of claim 1, wherein a fist oxide is formedabove the polysilicon layer and between a side of the polysilicon layerand a space of the n-type transistor.
 7. The device of claim 6, whereina deposited silicide on at least a portion of the polysilicon layer ofthe n-type field effect transistor comprises at least one of Co, HF, Mo,Ni, Pd₂, Pt, Ta, Ti, W, and Zr.
 8. An integrated circuit, comprising: ap-type transistor having a polysilicon layer; and an n-type transistorhaving a polysilicon gate, wherein, after oxidation of the polysilicongate of the n-type transistor, the polysilicon gate of the n-typetransistor has an oxide edge with the shape of a vertical bird's beakwhich tapers towards an uppermost surface, at least a portion of thepolysilicon gate and a portion of an oxide layer are present along aplane perpendicular to a plane of the base of the polysilicon gate andthe bird's beak is formed between the polysilicon gate of the n-typetransistor and a spacer of the n-type transistor.